The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (the number of interconnected devices per chip area) has generally increased while geometry size (the smallest component (or line) that can be created using a fabrication process) has decreased. In addition to providing benefits, this scaling down process has increased the complexity of processing and manufacturing ICs.
Logic circuits and embedded static random-access memory (SRAM) cells are frequently integrated into semiconductor devices for increased functional density. To meet the demand for higher SRAM density, simply scaling down the semiconductor feature size is no longer enough. For example, traditional SRAM cell structure with planar transistors has experienced degraded device performance and higher leakage when manufactured with smaller semiconductor geometries. One of the techniques for meeting such a challenge is to use three-dimensional transistors having a fin or multi-fin structure (e.g., Fin-FETs). To improve short channel control and area reduction, the fin structures are desired to be as thin as possible. One of the techniques for manufacturing thin fin structures is spacer lithography. For example, spacers are built on sidewalls of mandrel patterns. After the mandrel patterns are removed, the spacers become an etch mask for etching a silicon substrate in forming the fin structures. The dimensions of the mandrel patterns and spacers control the width and pitch of the fin structures. A tight control of critical dimension (CD) uniformity of the mandrel patterns and spacers is a design challenge for embedded Fin-FET SRAM.